Mate 60 and the SMIC Surprise

The chip arrived in a padded plastic case at TechInsights’ Ottawa laboratory in the first week of September 2023, less than seventy-two hours after a courier had purchased the phone in Shenzhen and another courier had carried it across the Pacific. The technical analysts unwrapped the Mate 60 Pro on a stainless workbench in a clean room at the firm’s Kanata facility, removed the back glass with a heated suction cup, and walked the application processor through the rituals that had grown up around the firm over twenty years of doing this work for chip-industry clients. They scanned the package. They desoldered the system-on-chip from the board. They decapsulated it with fuming nitric acid. They thinned the silicon down to a few hundred nanometers and slipped a sliver of it into a transmission electron microscope, where the gate and the contact and the lower metal layers came up onto the screen one after another in the gray reading light of high magnification. By the morning of September 4, a small slide deck was circulating to subscribers. The application processor was the HiSilicon Kirin 9000s. The die measured 107 square millimeters. It carried thirteen metal layers. The transistor pitches sat between SMIC’s 14-nanometer node and TSMC’s first-generation N7. There was no signature, anywhere in the cross-section, of an extreme ultraviolet exposure. The chip had been built on deep ultraviolet immersion scanners running multi-patterning sequences that the rest of the world had abandoned three nodes earlier as economically impractical. SMIC, on the evidence on the screen, had not abandoned them.

The political reaction had already saturated the news cycle. The technical question that mattered had not. Inside the analyst community, the conversation that opened that week and ran through the rest of the year was not whether SMIC had reached a 7-nanometer-class process. The TechInsights deck answered that. It was what the process had cost, how many wafers it could move per month, and how high it could go from there.

The first part of the answer turned on a particular piece of lithographic exotica called self-aligned quadruple patterning. Photolithography reaches its physical limits when the wavelength of the light used to expose a pattern becomes comparable to the smallest features being printed. For the deep-ultraviolet immersion scanners that ASML and Nikon had been shipping since the mid-2000s, the wavelength was 193 nanometers and the smallest single-exposure feature was around 38 nanometers, set by the diffraction limit of the optics. To print finer features, the industry had spent two decades inventing ways to get more than one effective exposure out of a single layer. Double patterning split a dense pattern into two coarser patterns, exposed sequentially, each at a relaxed pitch the optics could resolve. Quadruple patterning split it into four. The self-aligned variant used spacer materials deposited around a sacrificial mandrel and then etched away to leave behind features at one quarter of the original pitch, which was how, in principle, a 193-nanometer scanner could draw a 20-nanometer line. The catch was that every additional exposure multiplied the number of times the wafer had to be coated with photoresist, exposed, developed, etched, and stripped. A 7-nanometer logic layer that took roughly nine exposure steps with EUV took, by industry estimates, somewhere between thirty and thirty-four steps with DUV multi-patterning. Each additional step added defectivity, added cycle time, added equipment cost, and added the probability that a misalignment between exposures would translate into a dead transistor.

When the TechInsights team published its detailed back-end-of-line analysis in early October, the structural fingerprints of self-aligned multi-patterning were visible on slide after slide. The lower metal layers on the Kirin 9000s sat at pitches very close to TSMC’s N7 metals from 2018. The fin pitch and contacted poly pitch were in the same neighborhood. The die was a few percent larger than the Kirin 9000 that TSMC had fabricated for the Mate 40 Pro three years earlier on its 5-nanometer N5 process, which fit a node-and-a-half gap. None of that was unexpected. What was unexpected was that the cell library underneath looked like a serious commercial 7-nanometer design. SMIC had paired its multi-patterned process with a six-track standard cell, single-diffusion-break layout and a set of design-technology co-optimization features that, by TechInsights’ density estimates, pushed the node into the same logic-density neighborhood as TSMC N7 and Intel’s 10-nanometer process. As Dan Hutcheson, the firm’s vice chair and the elder statesman of the analyst community, put it in commentary that circulated for weeks, the most common Western mistake about Chinese capability had been the assumption that all DUV systems were created equal. They were not. With the right scanner, the right resist chemistry, the right metrology, the right thermal control, and a small army of process engineers willing to live with the rework rates, 193-nanometer immersion could in fact be pushed to a 7-nanometer node. SMIC, with Liang Mong-song’s stamina and Ren Zhengfei’s money behind it, had pushed.

What the chip on the bench in Ottawa did not show was the rest of the line. Behind every Kirin 9000s die that ran across the September 2023 launch, somewhere between three and five other die had likely failed in fabrication. Bloomberg’s reporting through the autumn, drawing on industry sources who had visited the SMIC fabs in Shanghai and Beijing, put the line yield somewhere in the band from twenty percent to fifty percent. Reuters’ Karen Freifeld, working a different set of sources, landed in the same range. Industry tracker counts that landed later in 2024 sharpened the picture: the most-cited estimates from semiconductor analysts put SMIC’s 7-nanometer yield at around fifteen to thirty percent during the 2023 ramp, climbing toward forty to fifty percent for the most stable parts of the line by mid-2024. TSMC, by comparison, had crossed seventy percent yield on its DUV-only first generation of N7 within roughly a year of high-volume production in 2018, and had pushed it above ninety percent by the time it migrated to EUV-assisted N7+ in 2019. The yield gap was the cost gap. SMIC’s wafer was reportedly priced to its largest customer, Huawei, at a forty-to-fifty-percent premium over what TSMC charged for the equivalent node. After accounting for the fraction of die that died in fab, the per-functional-die premium was higher still, in the rough neighborhood of two to three times.

The capacity question ran in parallel. SMIC did not break out node-level wafer starts in its earnings disclosures. Industry estimates assembled by SemiAnalysis, by the Japanese trade group counts, and by TrendForce sketched a picture in which the company’s 7-nanometer line at its Shanghai and Beijing fabs ran somewhere between twenty-five and fifty thousand wafers per month through 2024, with a stated ambition to roughly double that by the end of 2025. Even at the upper end of that range, total annual 7-nanometer wafer output was a fraction of what TSMC ran at the same node. TSMC’s Tainan and Hsinchu N7 lines, in their high-volume years, had crossed a hundred and forty thousand wafer starts per month. The gap was not just yield. It was throughput per scanner. Multi-patterning a 7-nanometer layer with quadruple exposure cuts effective scanner throughput compared to a single EUV exposure by a factor that varied with the layer but ran on the order of three to five. SMIC was running its scanners harder, and getting fewer salable die out of each wafer that passed under them, than the foreign competitor it was being compared against.

For Huawei, in 2023 and 2024, the math worked anyway. The Mate 60 Pro priced into the Chinese premium-smartphone market at 6,999 yuan, a price band where the gross margin was wide enough to absorb a chip cost two or three times TSMC’s. The customer was a captive Chinese consumer base willing, after five years of public sanctions narrative, to pay a premium for a domestic flagship and to wait through allocation queues to get one. The Mate 60 series sold something on the order of fifteen million units in its first six months and roughly thirty million across its first year, climbing through a Chinese market that Apple had owned at the top end since 2017. By the first quarter of 2024, on Counterpoint Research counts, Huawei had passed Apple in domestic Chinese smartphone share for the first time since the 2019 sanctions had forced its retreat. Qualcomm, which had quietly hoped to retain the high-end Chinese SoC business that the Kirin had vacated, watched its Snapdragon shipments to Chinese OEMs slip as Huawei’s domestic revival ate into the addressable market and as the other Chinese handset makers, watching the political weather, began signaling preference for HiSilicon and SMIC chips when they could get them.

The political response in Washington took shape over the autumn but did not, in October, reshape any rule already on the books. The technical question had already been settled. The chip on the TechInsights bench was a real 7-nanometer-class part, fabricated in commercial volumes, on Chinese soil. The remaining questions, the ones the rest of this chapter is about, were how cheap, how fast, and how high.

Eight months later, the Pura 70 launched, and the answers to those questions began to arrive.

On April 18, 2024, Huawei’s website opened pre-orders for the Pura 70 line, the company’s repositioned successor to the P-series that had once anchored its non-Mate flagship slot. The chip inside was the HiSilicon Kirin 9010. Within ten days, TechInsights had a Pura 70 Ultra on the bench in Ottawa and another slide deck on its subscriber portal. The verdict was both reassuring and unflattering. The Kirin 9010, the deck reported, was substantially the same processor as the Kirin 9000s, fabricated on the same SMIC N+2 7-nanometer process node, with what looked like a revised circuit floorplan aimed primarily at improving yield rather than at advancing the underlying technology. The model number etched into the die was, on iFixit’s later teardown, identical to the Kirin 9000s — Hi36A0 — with the only physical distinction a one-character revision suffix. Performance gains over the Kirin 9000s, on standard benchmarks, ran in the single digits. The Cortex efficiency cores ran a few hundred megahertz higher. The Taishan performance cores were marginally faster. Power efficiency was modestly improved. None of it amounted to a node transition. The reasonable read was that SMIC had not been able to bring up an N+3 process inside the eight months between the two phone launches and that Huawei, faced with the choice between ship a respin and ship nothing, had shipped a respin. Hutcheson’s framing was characteristically dry. Huawei, he said, had broken free of U.S. sanctions inside China’s market. It was still being held back by U.S. sanctions outside it.

The framing inside the Chinese supply chain that spring was even tighter. SMIC’s 7-nanometer line was capacity-constrained. Both the Mate 60 series and the Pura 70 series sold out in waves through 2024, with periodic supply shortages that no amount of state subsidy could close. The Pura 70 hit allocation limits within hours of opening pre-orders and the resale market in Shenzhen reportedly priced units thirty to forty percent above list. Industry reporting at the time, including by iFixit’s analysts and by SCMP correspondents working Hubei suppliers, attributed the shortages to the underlying yield mathematics. If SMIC was getting twenty to thirty good die out of every hundred attempted, and if the Beijing and Shanghai 7-nanometer fabs together ran at most fifty thousand wafer starts per month, then the upper bound on annual Kirin 9010 output sat somewhere in the low tens of millions, not the high tens of millions that Qualcomm or MediaTek could have shipped on TSMC’s N4 or N5 lines without sanction. Huawei’s 2024 smartphone shipment recovery, real and substantial as it was, was running into the silicon ceiling of the foundry that supported it.

What it could not do, that the Pura 70 launch made clear, was move down a node. There were rumors, at the moment of the April launch, that SMIC was preparing a 5-nanometer process for a future Huawei flagship. The technical literature on what such a process would look like, on the equipment SMIC had on hand, was unsparing. To extend deep-ultraviolet immersion lithography from 7 nanometers to 5 nanometers without EUV, the multi-patterning sequence has to be doubled again, from quadruple to octuple in some published academic flow proposals, or at minimum extended with self-aligned-litho-etch-litho-etch sequences whose exposure-step counts run upwards of forty per critical layer. IBM’s published comparisons of high-numerical-aperture EUV against multi-pass DUV at the same node, written into the 2025 SPIE conference proceedings, put the relative cost of a four-mask SALELE process at 1.7 to 2.1 times that of a single high-NA EUV pass. At eight masks, the relative cost passed 4x. The defect rates compounded faster than the per-mask cost. In any sober yield-modeling exercise the industry had run on the topic, a DUV-only 5-nanometer process delivered single-digit wafer yields on its first generation, with no obvious path to climbing through ramp-up the way TSMC’s N7 had. The reason TSMC had moved to EUV at 7-nanometer-plus had been precisely this calculation: every additional patterning step bought a smaller and smaller density gain at a larger and larger cost.

The Mate 70, when it arrived seven months after the Pura 70, confirmed the diagnosis. Huawei opened orders for the Mate 70 series on November 26, 2024, at a brand event in Shanghai that doubled as the public launch of HarmonyOS Next, the company’s newly de-Androided operating system. The chip inside was the Kirin 9020. It was, again, fabricated by SMIC. It was, again, on the same N+2 7-nanometer node. TechInsights’ teardown reached the firm’s subscribers in early December. Alexandra Noguera, one of the firm’s circuit analysts, told the wire press that the Kirin 9020 was not a major redesign of the Kirin line. The die had grown by roughly fifteen percent over the Kirin 9010. The architecture had shifted slightly: two high-frequency Taishan cores at 2.5 gigahertz, six mid-frequency cores at 2.15, four efficiency cores at 1.6, on a clock topology that resembled a slightly retuned 9010 more than a wholly new SoC. Performance gains, on benchmarks circulated by Chinese reviewers, ran in the same single-digit range that had separated the 9010 from the 9000s. Three flagship launches in fifteen months — Mate 60 in August 2023, Pura 70 in April 2024, Mate 70 in November 2024 — had moved Huawei across three product cycles on a single SMIC process node. The climb that the Mate 60 Pro had announced had, somewhere between Pura 70 and Mate 70, become a plateau.

This was, by mid-decade, the shape of the Chinese leading-edge story that the Mate 60 Pro had opened. SMIC had reached a 7-nanometer-class node without EUV. The chip in the phone proved it. The chip in the next phone, and the phone after that, proved the node was staying where it was. Yields were tolerable but not good, costs were higher than TSMC’s by a factor that mattered for AI accelerators and was absorbable for premium smartphones, capacity was real but bounded. By any technical reading anyone in the industry trusted, the ceiling was not a 5-nanometer DUV-only process that would let the climb continue in 2025 or 2026 without an EUV machine the Netherlands was not going to ship.

What that left was a stable but uncomfortable mid-decade equilibrium. China had a domestic 7-nanometer logic node. China shipped products on it. China could not, from that node, move forward without either an EUV scanner from Veldhoven, a domestic EUV scanner that Shanghai Micro Electronics was years away from delivering at production grade, or a fundamentally different patterning architecture that no one anywhere in the industry had publicly demonstrated. The corollary was symmetric. The United States had drawn an export-control perimeter that could prevent China from buying its way to the next node. It could not, on the evidence of the Kirin 9000s and its successors, prevent China from building products on the node it had already reached, or from supplying its own domestic market with handsets and base stations and increasingly AI-adjacent chips that the world’s leading-edge fabs would no longer make for it.

Both sides had learned something from the Mate 60 Pro launch. Beijing had learned that aggressive multi-patterning could carry a Chinese fab one node past where Western analysts had thought sanctions would freeze it. Washington had learned that the chip war’s first real test had not produced the cliff its drafters might have expected and instead had produced a slow grind, in which a Chinese foundry under sanctions could still ship a flagship-grade smartphone processor, just not the next one, and not the one after that, without a tool the West controlled. The technical question of where exactly the climb stalled, and the political question of how long the stall would last, would dominate the next year of export-control argument. They would also, beneath the smartphone news, begin to converge with a different and larger problem. The chips inside the next class of products that Beijing wanted to build, the AI accelerators meant to compete with Nvidia’s H100s in training runs that the United States had already moved to deny, would be built on this same SMIC 7-nanometer line. The yield, the cost, and the ceiling that the Mate 60 Pro had revealed were about to matter for something larger than handsets.