How Intel Forgot Innovation

On June 4, 2024, in a convention hall in Taipei, Pat Gelsinger held up a small rectangle of silicon and admitted, in front of an audience of customers and reporters and rivals, that the chip in his hand had not been made in an Intel fab. The rectangle was the compute tile of Intel’s new mobile processor, code-named Lunar Lake. It contained the cores, the graphics, and the neural accelerator that would define the next generation of x86 laptops. Gelsinger explained that for this product, Intel had selected an external foundry partner, and the partner was TSMC, on its three-nanometer N3B node. The choice, he said, came down to which process technology was best for the design at the time the design had to be locked. TSMC, at that point, had been better. So Intel had bought from TSMC.

He delivered the line gracefully. The audience, which included Morris Chang’s successors and a gallery of Taiwanese press, applauded politely. Outside the ballroom, the implications were less polite. The chief executive of the company that had taught the industry how to make leading-edge logic was telling the world, on Taiwanese soil, that the leading-edge logic in his flagship laptop part had been made by somebody else.

To understand how Intel got to that ballroom, the timeline has to start a decade earlier, with a different chief executive holding a different chip and saying something nobody yet had reason to disbelieve.

Brian Krzanich took over as Intel’s sixth chief executive on May 16, 2013, at the company’s annual meeting in Santa Clara. He had joined Intel as a process engineer in 1982 and risen through the manufacturing organization. He had run a fab in Massachusetts, then the global factory network, then become chief operating officer in January 2012. The board’s logic in elevating him was that the company’s identity was its process. Paul Otellini, Krzanich’s predecessor, had been a sales executive who had ridden Intel’s manufacturing lead into one of the most profitable franchises in business. The board wanted somebody who understood the part of the franchise that had been doing the riding.

The franchise had a name, and the name was tick-tock. Since 2007 Intel had alternated, year by year, between a “tick” that shrank an existing microarchitecture onto a new process node, and a “tock” that introduced a new microarchitecture on the now-mature node. The cadence was famous inside the industry because no one else managed it. Through 22-nanometer Ivy Bridge in 2012 and 22-nanometer Haswell in 2013, Intel was running the most disciplined product roadmap in semiconductors. The next node, 14 nanometers, was supposed to land in the second half of 2013 with the Broadwell tick. Krzanich’s first months as CEO would carry it across the line.

The line moved. In a press briefing on October 15, 2013, Krzanich told reporters that Broadwell production was being pushed into the first quarter of 2014. The reason, he said, was an issue of defect density on the 14-nanometer process. The fixes that worked in the development line were not converging fast enough on the production line. He framed the problem as routine, the kind of bump that happened in the late stages of a node, and said it had been resolved. “It’s simply a defect density issue,” Krzanich told The Register. “As we develop these technologies, what you do is continually improve the defect densities and they result in the yield, the number of dies per wafer.”

Inside the company, the picture was less casual. Intel had set internal yield targets that the production teams could not hit. The first 14-nanometer Broadwell parts, two-core mobile chips for ultrabooks, would not begin shipping in volume until late 2014, more than a year after the original schedule. Higher-power desktop and server variants slipped further. The tick had broken.

The tock that followed, Skylake, made it to market on time on the same node in August 2015 with a new microarchitecture and a respectable showing. But the next tick, the move to 10 nanometers, was the one that changed Intel’s relationship with its own roadmap.

The 10-nanometer node, internally known as 1274, was the most ambitious process Intel had ever attempted. Mark Bohr, the senior fellow who had become the public face of Intel’s process technology, had laid out the plan at the company’s Technology and Manufacturing Day in March 2017. Where competitors were moving from their 16- or 14-nanometer nodes to a 10-nanometer node that delivered roughly twice the transistor density, Intel intended to deliver a 2.7x density jump, from 37.5 million transistors per square millimeter to more than 100 million. To make the jump, the process used self-aligned quad patterning on critical layers, a four-step optical exposure that broke a single feature into multiple passes. It also introduced cobalt as the metal in the lowest two layers of the interconnect stack, replacing tungsten, on the theory that cobalt’s lower resistance and better electromigration tolerance would let the wires hold up at the new dimensions.

On paper the gamble was elegant. Intel would skip a half-step that competitors took for granted and arrive at a node that was, by Bohr’s metric, more than twice as dense as anything TSMC or Samsung had announced for their own 10-nanometer offerings. In practice each of the gambles compounded. Self-aligned quad patterning multiplied the lithography variability across the wafer. Cobalt was a new material in volume manufacturing, and its electroplating, polishing, and inspection demanded tooling and recipes that Intel had not built before. The production teams discovered defects in places where their decades of tungsten-and-copper experience offered no diagnostic vocabulary.

The original plan had been to ship 10-nanometer Cannon Lake parts in the second half of 2016. The slip, when it came, was not announced as a single dramatic delay but as a slow leak across earnings calls. The 2016 ship date became 2017. The 2017 date became “second half 2018.” Inside the press, the running joke was that Intel’s 10-nanometer ship date was a function of the fiscal calendar, not the silicon. When Cannon Lake finally arrived, in the spring of 2018, it arrived in the most embarrassing form Intel could have invented for it. The single retail product that contained a 10-nanometer Cannon Lake chip was a Chinese-market Lenovo Ideapad 330 laptop fitted with a two-core Core i3-8121U whose integrated graphics had been physically disabled because the on-die GPU did not work. Intel followed with a small NUC desktop kit, code-named Crimson Canyon, that paired the same crippled CPU with a discrete AMD graphics chip. By volume, the 10-nanometer Cannon Lake program had launched and ended in a single SKU.

The deeper humiliation was that Intel’s customers and competitors had spent the years between 2015 and 2018 watching another company close the manufacturing gap that Intel believed could not be closed. TSMC had begun risk production of its 7-nanometer node in 2017, ramped to volume through 2018, and shipped the Apple A12 Bionic in iPhones that fall. By Bohr’s own density metric, TSMC’s 7-nanometer node was approximately equivalent to Intel’s 10-nanometer node. By the cruder metric of which one was actually in customers’ hands, TSMC was now ahead. AMD had quietly begun designing its Ryzen processors against TSMC’s roadmap. Apple, having shipped iPhones on TSMC since 2014, was building toward a Mac transition. The fabless ecosystem had decided which manufacturer it trusted, and the decision was not Bedford 1985’s GCA story all over again only because there was no Bedford. It was happening inside Intel itself.

Bohr fought the rearguard. Through 2017 and into 2018, he argued that the industry’s nanometer labels had become marketing fictions: TSMC’s “7-nanometer” and Intel’s “10-nanometer” referred to processes with similar density and performance, and Intel’s was the more technically ambitious of the two. He proposed that the industry adopt a transistor-density metric expressed in millions of transistors per square millimeter. The proposal was technically defensible. It also looked, to most observers outside Intel, like a man explaining why his late train had really arrived first, if you measured punctuality differently.

Inside the lithography stack, the second misstep was about a tool Intel had decided not to buy. Through the 2010s, ASML in Veldhoven had been pushing extreme ultraviolet lithography, EUV, from a long laboratory program toward production status. By 2017, ASML’s EUV scanners were close enough to volume that TSMC and Samsung had begun designing their next-generation nodes around them. Intel, which had been one of EUV’s earliest backers and had taken an equity stake in ASML in 2012 to help fund the program, had decided that its 10-nanometer node would not use EUV. The reasoning, articulated in numerous briefings, was that EUV was not yet ready, that the throughput was too low, that the source power was insufficient, and that Intel’s existing 193-nanometer immersion tooling, augmented by quad patterning, could carry the company through 10-nanometer and into 7-nanometer with no productivity penalty. The judgment was defensible at the time it was made. It became a strategic disaster as TSMC pulled EUV into volume on its 7+ and then its 5-nanometer nodes through 2019 and 2020. Intel, having insisted that EUV was not yet ready, found itself pinned to a multi-patterning stack that was the actual source of its 10-nanometer yield problems.

The personnel story moved in parallel. On June 21, 2018, with 10-nanometer late and the press cycle ugly, Intel’s board announced that Krzanich was resigning, effective immediately. The stated reason was a violation of the company’s non-fraternization policy through a past consensual relationship with a subordinate. The relationship was reportedly old and had ended, but the policy was the policy, and the board chose to enforce it. Inside Intel, the fraternization line was widely understood to be the official rationale for a decision the board would have struggled to justify on the manufacturing record alone. Either way, Krzanich was out. The chief financial officer, Bob Swan, was named interim chief executive while the board ran a search.

The search ended six months later with the announcement that Swan, the finance executive who had joined Intel from General Atlantic in 2016, was being made the permanent CEO. Swan had been a CFO at eBay and General Electric before Intel, and he was, by every available measure, an excellent finance executive. He was also the first person to run Intel without a fab tour somewhere on his résumé. The board’s choice, made in the aftermath of Krzanich’s exit and against a slate of more technical candidates, was the second clear signal in five years that the directors had concluded the manufacturing problem was a problem of management discipline rather than of engineering judgment. The first signal had been Krzanich’s elevation in 2013. The second was Swan’s confirmation in early 2019.

Then came the call.

On July 23, 2020, on Intel’s second-quarter earnings call, Swan told analysts that 7-nanometer, the node that was supposed to follow 10-nanometer and bring Intel back into process leadership, was running approximately twelve months behind its yield target. Initial product shipments, originally guided to late 2021, would now slip to late 2022 or early 2023. The cause, Swan said, was a defect mode that had been identified and was being corrected, but the schedule effect was real. Intel was prepared, he added, to use third-party foundries to manufacture some of its products if necessary. “We will use somebody else’s process technology, and we’ll call it ours, or theirs,” Swan said. The market understood what they had heard. Intel’s stock fell roughly 16 percent the next day. AMD’s rose 8 percent.

Six days later, on July 27, Murthy Renduchintala, the executive who as Intel’s chief engineering officer had been responsible for both the 10-nanometer and 7-nanometer programs, was announced as departing. Intel said it would not refill his role; the engineering organization would be split into five separate teams, each reporting directly to the CEO. Ann Kelleher, who had previously run Intel’s 10-nanometer manufacturing ramp, was given charge of the 7-nanometer and 5-nanometer development. The reorganization was the kind of structural overhaul that companies typically perform after the third or fourth crisis, not the first. Intel by the summer of 2020 had passed any reasonable count of how many crises this was.

It was in the weeks after that earnings call that the case for changing the chief executive again moved from analyst commentary to investor demand. In December 2020, the activist hedge fund Third Point, run by Daniel Loeb, sent Intel’s chairman a letter calling for “strategic alternatives” including a separation of design and manufacturing. By early January 2021, the board had concluded that Swan would not be the person to lead the response. On January 13, Intel announced that Pat Gelsinger, then the chief executive of VMware, would return as Intel’s CEO on February 15, replacing Swan.

Gelsinger’s return was, by the standards of corporate succession, deeply emotional. He had joined Intel at eighteen years old in 1979, an associate-degree graduate from Lincoln Tech. He had been employee number four on the 386 design team that Andy Grove had bet the company on in 1985. Grove had personally mentored him. Gelsinger had risen to chief technology officer in 2001, the youngest in Intel’s history, and then in 2009, after losing an internal succession contest to Otellini’s allies, had left for EMC and then VMware. He spent the 2010s building VMware into one of the most consequential infrastructure software companies in the industry. When the call came in late 2020, he was 59, a self-described evangelical Christian who quoted Proverbs in his speeches and had once said publicly that running Intel one day was the closest thing he had to a vocational dream. He took the job.

On March 23, 2021, five weeks after he started, Gelsinger laid out his plan. The setting was a webcast he titled “Intel Unleashed: Engineering the Future.” The plan he presented was branded “IDM 2.0,” for integrated device manufacturer, the model Intel had pioneered and that Gelsinger now intended to extend rather than abandon. Intel would continue to design and manufacture its own chips. It would also, for the first time in a serious way, open its fabs to outside customers as a foundry. A new business unit, Intel Foundry Services, would be carved out and led by Randhir Thakur, reporting directly to Gelsinger. Intel would invest twenty billion dollars in two new fabs in Arizona, the first major US fab announcement in years. The company would also begin using TSMC capacity for some of its own products in the interim, an admission of the manufacturing gap recast as a “pragmatic” multi-vendor sourcing strategy.

The most aggressive line in the plan was the process roadmap. Gelsinger committed publicly that Intel would deliver “five nodes in four years”: Intel 7 (the renamed and improved 10-nanometer node), Intel 4, Intel 3, Intel 20A, and Intel 18A, the last two using a new transistor architecture called RibbonFET and a backside power-delivery scheme called PowerVia. The cadence was harder than anything Intel had managed since tick-tock had broken. Industry observers, who had spent a decade watching Intel miss schedules, called the plan ambitious to the point of recklessness. Gelsinger framed it as the only credible answer. Either Intel restored process leadership in this cycle or it would not have another cycle in which to do it.

For about two years, the recovery story held. Intel 7 ramped through 2021 and 2022 in Alder Lake and Sapphire Rapids, products that AMD’s competing Ryzen 7000 series outperformed in many benchmarks but that at least let Intel hold its server share through enterprise inertia. The renaming of the nodes, derided when announced in July 2021 as a marketing dodge, served its actual purpose: it cleared the rhetorical air so customers could compare Intel’s offerings to TSMC’s and Samsung’s on density and performance rather than on numerical labels that had stopped tracking anything physical. Intel signed up Qualcomm and Amazon Web Services as foundry customers for future nodes. The CHIPS and Science Act, signed by President Biden in August 2022, included $52 billion in semiconductor incentives whose largest single recipient, the political logic suggested, would be Intel.

Then the math caught up. Through 2023 and into 2024, Intel’s revenue declined as data-center demand softened, AMD’s server share grew, and the company’s capital spending on the new fabs dwarfed what the foundry business was earning. In April 2024, when Intel changed its accounting to disclose the foundry as a separate operating segment, the numbers it released startled the market: the foundry business had lost approximately seven billion dollars in 2023 on revenue of just under nineteen billion dollars. The internal Intel product groups had been paying transfer prices to the foundry that masked the structural unprofitability of running fabs at the volumes Intel was running them at. Disaggregated, the manufacturing operation was deeply underwater.

The Lunar Lake decision had been made before that disclosure became public, but in retrospect it read like a confession of the same problem. Intel’s mobile design team, faced with a launch window in mid-2024 and a roadmap in which Intel 18A would not be ready and Intel 4 was ramping but not yet competitive at the power efficiency Lunar Lake required, chose TSMC’s N3B as the manufacturing partner for the entire compute tile. The decision was urgent and, by every long-run measure, devastating. Goldman Sachs estimated that Intel’s payments to TSMC would total roughly 5.6 billion dollars in 2024 and nearly ten billion in 2025. Every dollar of those payments was a dollar that funded TSMC’s process lead and starved the case for Intel’s own fabs.

On September 16, 2024, after a board meeting that several reports later described as bruising, Intel announced that the foundry would be reorganized as a wholly-owned subsidiary with its own board of directors, an arrangement designed to allow outside investment without a formal spinoff. The structure was the breakup that Ben Thompson had argued for in his Stratechery analysis a year earlier and that Third Point had implicitly demanded in 2020, with one step held back. The board had not used the word breakup, but the plumbing was now in place if it ever wanted to.

Two and a half months later, on December 1, 2024, the board concluded that the man who had laid the plumbing would not be running it. Intel announced that Gelsinger had retired as CEO and as a member of the board, effective the same day. The official statement spoke of the work he had begun and the foundation he had laid. The reporting that followed, in Bloomberg and the Wall Street Journal, made clear that the board’s confidence in his ability to deliver the turnaround had collapsed. David Zinsner, the chief financial officer, and Michelle Johnston Holthaus, head of Intel’s products business, were named interim co-chief executives while the search began. In March 2025, the board chose Lip-Bu Tan, the former chief executive of Cadence Design Systems and a longtime venture investor in semiconductor companies, as the next CEO. Tan, by some accounts, had originally turned the role down before taking it on the second ask.

Tan inherited a company whose factories were running a node, Intel 18A, that was technically credible but commercially uncertain. Through 2025 he pushed yield improvements at a pace his teams described as relentless. He pruned roadmap plans Gelsinger had built, including a high-cost glass-substrate program. He went looking for a marquee external customer for 18A, then 14A, the only thing that could make the foundry mathematically work. As of 2026 the search for that customer is unfinished.

What had broken inside Intel was not, in the end, the specific decisions about cobalt or quad patterning or EUV, though those decisions had each cost the company a year. What had broken was the conviction that Intel’s manufacturing process was an inheritance the engineers and managers were entitled to receive in working order, a thing the calendar would deliver if you simply waited. For three decades that conviction had been validated by the silicon. The conviction had survived Krzanich, then Swan, then most of Gelsinger’s tenure, because each crisis had been narrated as the last one.

The chip Pat Gelsinger held up in Taipei in June 2024 was the first artifact of the new arrangement, in which Intel was a customer of the manufacturing leader rather than the manufacturing leader itself. Whether the new arrangement would prove temporary or permanent depended on a node, 18A or 14A, that had not yet shipped, and on a customer the company had not yet named. The certainty about Intel that had defined the industry for thirty years was gone. What replaced it had not yet been written.