Running Faster?

In late October 2017, in a Bloomberg interview given a few months after he had announced he would step down as TSMC’s chairman the following June, Morris Chang took the trouble to put a number on what was coming. He had done the calculation himself, the way he liked to do calculations, with a pencil and a yellow pad and the patience of a man who had been pricing chip economics for fifty years. The 3-nanometer fab the company had been quietly designing, the next leap beyond the 5-nanometer facility already rising on the southern Taiwan plain, would cost, when all the necessary capacity had been built, somewhere upwards of fifteen billion dollars. He paused, characteristically, before committing to the higher figure. Maybe it was safer, he said, to call it twenty.

The number, when it landed in Bloomberg’s wire feed and from there into the headlines of every Asian business paper that night, did not surprise anyone in the industry. Inside TSMC’s planning meetings, the working assumption had been north of fifteen for two years. What was novel was Chang saying it on the record. The chairman was telling the world, in the careful diction of an octogenarian who had long since stopped saying things he did not mean, that a single new factory, producing chips for a single new generation of process technology, would cost as much as the entire annual research and development budget of the United States Air Force. He was telling the world that the industry he had founded thirty years earlier was now built on capital expenditures that no government department, and almost no other company, could underwrite.

The number was not the whole story. The number was the headline. The deeper story sat in a relationship between two slopes that the industry had been watching since the early 1970s, and that had begun, by 2017, to look genuinely menacing.

The first slope was Moore’s Law. Gordon Moore, in his 1965 Electronics article, had observed that the number of components economically integrable on a single chip was doubling roughly every year, and would, for at least the next decade, keep doubling. He revised the rate to two years in 1975. The doubling held. It had held, to a remarkable approximation, for half a century. Each new generation of semiconductor process, labeled by what was nominally a feature size in microns and then in nanometers, although by the late 2000s the labels had become marketing fiction more than physical measurement, packed twice the transistors into the same area. Each generation, in turn, made cheaper computing possible.

The second slope was Rock’s Law. Arthur Rock, the venture capitalist who had assembled the financing for Fairchild and then for Intel, who had served as Intel’s first chairman, and who had spent the first decade of the company’s life sitting in board meetings watching Gordon Moore’s curves and Andy Grove’s spreadsheets, had observed something Moore had not foregrounded. The capital cost of a state-of-the-art fab was itself doubling, on a slower clock of roughly every four years. Moore later attributed the observation publicly to Rock, sometimes calling it Moore’s Second Law and sometimes Rock’s Law, and the joke, inside the boardrooms that lived under it, was that the second law would eventually kill the first. Two slopes were running in opposite economic directions. Transistors were getting cheaper. The factories that made them were getting more expensive. Sooner or later, one curve would have to bend.

For three decades, the curves had cooperated. A new fab in 1980 cost something on the order of $200 million, and the chips it produced sold for enough to pay it back. By the early 1990s, a new fab cost $1 billion, and Intel and the Japanese DRAM makers could still amortize that across their volumes. By the time Moore stood in front of the SPIE microlithography conference in February 1995 to deliver the speech later published as “Lithography and the Future of Moore’s Law,” he was projecting that state-of-the-art fabs would cost over $2 billion that year and roughly $3 billion by the end of the decade. He did not pretend to know how the industry would keep affording the curve. The closing line of his paper had become quietly famous in the years since: the rate of technological progress, Moore had said, was going to be controlled from financial realities. He had said it with the flat affect of an engineer who had seen the spreadsheet and was reporting what he saw.

By 2017, when Chang put a $20 billion sticker on the 3nm fab, the second slope had not bent. It had steepened.

The reason was lithography. The trick that had carried the industry for forty years, printing successively smaller patterns onto silicon wafers using projected light, had been running into the wavelength of the light itself for at least the past two decades. By the early 2000s, the steppers used in production were already projecting at 193 nanometers, down from 248. To etch features finer than the wavelength they were using, the engineers had been forced to invent successively more elaborate workarounds. Phase-shift masks had bought a generation. Liquid-immersion lithography, in which a thin film of water between the lens and the wafer effectively raised the lens’s numerical aperture, had bought another. Multi-patterning, in which the same pattern was painted onto the wafer in two or three or four exposures with submicron alignment, had bought several more, at the cost of dramatically increased process steps, mask counts, and defectivity. Each generation cost more passes, more masks, more time, more equipment, and more rework. The industry was running faster on the same treadmill.

The end of that road had been visible since at least the mid-1990s. The next light source had to be much shorter than 193 nanometers. The candidates had narrowed quickly to extreme ultraviolet, at 13.5 nanometers, an energy regime in which no lens material on Earth could focus the beam, so every optic had to be a multilayer mirror, and in which the source itself had to be a plasma generated by zapping tin droplets with a megawatt-class CO2 laser inside a vacuum chamber. The Dutch firm ASML had been working on EUV since the late 1990s, in a research program funded by Intel, Samsung, and TSMC, and the machine was, as the engineers who lived inside it joked, the most complicated tool any human civilization had ever attempted to manufacture in volume. By the time it began entering production fabs in 2018 and 2019, a single low-numerical-aperture EUV scanner was carrying a list price of around $180 million. The next-generation high-NA tools, which began shipping a few years later, were priced near $380 million. ASML was the only company in the world that made them. Without an EUV scanner, a fab could not make chips at 7 nanometers and below.

This was the engine driving Rock’s Law into the steepening curve that Chang’s $20 billion fab represented. A leading-edge facility now needed to host, in its cleanrooms, a small fleet of EUV machines, usually somewhere between ten and twenty for a fully tooled fab, each costing more than a Boeing 737 and weighing about as much. It needed thousands of additional pieces of process equipment from Applied Materials, Lam Research, Tokyo Electron, KLA, and dozens of smaller specialist vendors, each generation of which was itself more expensive than the last. The cleanroom itself, the building, the air handling systems, the pure-water plant, the chemical distribution, the abatement systems, the metrology equipment, and the tens of millions of square feet of subfab utility space wrapped around the production floor each ran into the hundreds of millions or billions of dollars before a single wafer had moved through. A 28-nanometer fab, in the early 2010s, was a $3 to $5 billion project. A 7-nanometer fab, from about 2018, was a $10 to $15 billion project. A 3-nanometer fab, by 2020, was a $15 to $20 billion project, with the high end pushing $30 billion if a chipmaker was doing it for the first time outside Asia.

The capex was only one column on the spreadsheet. The other column, less visible to outsiders but increasingly decisive, was design.

For most of the industry’s history, design costs had been a manageable fraction of total project economics. A new chip on a mature process, 130 nanometers in 2002 or 90 nanometers in 2004, cost a few tens of millions of dollars to design, verify, and tape out. The mask set, the array of quartz plates carrying the patterns the lithography tools would project, was perhaps half a million dollars. A startup with twenty engineers and a Series B round could afford a tape-out and would still have money left over to ship product.

By the late 2010s, those numbers had broken. According to figures compiled by the consultancy International Business Strategies, run by a long-time industry analyst named Handel Jones, an average chip designed at 28 nanometers cost about $40 million in development. The same chip, scaled to 16 or 14 nanometers using FinFET transistors, cost roughly $100 million. At 7 nanometers, where EUV first showed up in production at TSMC for Apple’s A12 in the 2018 iPhones, design cost roughly $217 million. At 5 nanometers, $416 million. At 3 nanometers, the IBS estimate was $590 million per design. The cost of a single mask set had risen from a million dollars at 28 nanometers to ten million at 7 nanometers to something in the $30 to $40 million range at 3 nanometers. A single tape-out, the moment a designer committed a year’s work to a fab and waited three months to see whether the chip even powered on, could cost $100 million by itself before the bring-up team had ever opened a logic analyzer.

The largest piece of the design cost, by far, was not the mask. It was verification. As the transistor counts on a single chip climbed past ten billion, then past fifty billion, the number of possible internal states grew faster than any direct simulation could check. Hardware designers had spent the previous two decades inventing increasingly elaborate ways to convince themselves that a chip would work, with formal methods, emulation farms, constrained random testing, and post-silicon debug, and each generation of tooling cost more than the last. Intel’s experience with its own modern processors offered a public glimpse of how brutal the curve had become. Its Ice Lake server chip, first powered on in December 2018, took six full design revisions and almost three years to ship in volume. Its Sapphire Rapids successor, first powered on in June 2020, had taken twelve steppings by mid-2022 and was still being revised. Each of those steppings was a multi-month, eight-figure rerun of the entire fab cycle. The price of a single bug, found late, was now a meaningful fraction of a small country’s defense budget.

The economics of the second slope, in other words, were not just about the fab. They were about the entire stack required to use the fab. A company that wanted to ship a chip on the leading edge had to underwrite a $20 billion factory at a foundry, plus a $400 million design effort with hundreds of engineers, plus a $100 million tape-out gamble, plus a multi-year verification campaign, plus a software and IP ecosystem ready to absorb the result. The unit economics worked only if the design then sold in tens or hundreds of millions of units. There were, by the late 2010s, only a handful of products in the world that did. iPhones, certain GPUs, AMD’s CPUs, Qualcomm’s modems, a small number of network switch chips, a small number of AI accelerators. For everyone else, the leading edge had stopped being affordable.

The consolidation that followed was sharp and visible.

Through the 1990s and 2000s, a serious leading-edge logic process had been built by perhaps a dozen companies, depending on how generous one was with the definition. IBM had run its own fabs. Motorola had run its own fabs, then spun them off as Freescale. Texas Instruments had backed away from the leading edge in the early 2000s and shifted to analog and embedded. Sony, Toshiba, and IBM had collaborated on the Cell processor for the PlayStation 3 at IBM’s East Fishkill fab, and that joint effort had effectively been IBM’s last full-bore attempt to stay on the bleeding edge of logic. By 2014 IBM had paid GlobalFoundries $1.5 billion to take its semiconductor manufacturing operation off its hands.

GlobalFoundries had been spun out of AMD in 2009, when Hector Ruiz and Dirk Meyer had finally accepted that AMD could not afford to operate its own fabs against the rising capex curve, and had restructured the company as a fabless designer with the Abu Dhabi sovereign wealth fund picking up the manufacturing assets. For nearly a decade, GlobalFoundries had tried to keep up. It had bought IBM’s fabs to absorb their process knowledge. It had announced a 7-nanometer roadmap. It had begun installing EUV-compatible infrastructure at its Malta, New York, facility.

On the morning of August 27, 2018, the company’s then-chief executive Tom Caulfield, an IBM veteran who had been on the job for six months, called a press briefing to announce that GlobalFoundries was halting its 7-nanometer development indefinitely. The math, Caulfield explained, did not close. To build a 7-nanometer fab capable of running at the 40,000 to 50,000 wafers per month it would take to earn back the investment, the company would have to commit between $2 and $4 billion on top of what it had already spent. The customer base willing to pay for that capacity had narrowed to a handful of companies, every one of which had a primary or secondary relationship with TSMC. The expected return, Caulfield said in the careful language of a man who had run the numbers in a corner office for a long time, did not justify the spend. The company would refocus on differentiated specialty processes in RF, embedded memory, and automotive, at 14 nanometers and above. AMD, GlobalFoundries’ largest 7-nanometer customer, immediately rerouted its next-generation Ryzen and EPYC processors to TSMC.

Within a year, United Microelectronics Corporation, Taiwan’s number-two foundry, which had been chasing TSMC for two decades, formally confirmed what it had quietly admitted in 2017. UMC would not pursue process nodes below 14 nanometers. The required investment, the company’s chairman told reporters, could not be paid back from the addressable market UMC could realistically serve.

The result was a club of three. TSMC, Samsung, and Intel were the only companies still operating leading-edge logic processes by the time the 5-nanometer node entered production in 2020. Of those three, TSMC was a foundry serving everyone, Samsung was both a foundry and an internal customer for its own designs, and Intel was an integrated device manufacturer that had begun, around 2010, to slip behind on its own scaling roadmap and would by the late 2010s be visibly trailing both. By the time of Chang’s $20 billion comment, TSMC was running well over half of all foundry revenue worldwide, and over the next several years its share would climb past two thirds.

The same consolidation had played out, for the same reasons, in memory. The DRAM industry, which had been a thicket of producers in the 1980s and a smaller thicket in the 1990s, had narrowed to a handful by the 2010s. Elpida, Japan’s last surviving DRAM maker, had filed for bankruptcy in February 2012 and been acquired the following year by Micron. Hynix, the wounded Korean memory maker that had spent the early 2000s on the brink of insolvency, had been bought by SK Telecom in 2012 and rebranded as SK Hynix. By 2015, the global DRAM industry consisted, in any meaningful sense, of three companies: Samsung, SK Hynix, and Micron. The same three would, a few years later, be the only producers of high-bandwidth memory for AI accelerators, holding among them effectively all of the world’s capacity. The capex curve had done in memory what it would do in logic. It had selected for the largest survivors and erased everyone else.

Behind the consolidation lay a quieter physical truth: the transistor itself was running out of room. The planar MOSFET that had carried the industry from the 1960s through the 2000s had been replaced, around 2011, by Intel’s three-dimensional FinFET, in which the channel rose out of the silicon as a vertical fin rather than lying flat. FinFET had given the industry roughly another decade. By the late 2010s, the fins themselves were running into the same gate-control problems that had killed the planar device. The next architecture, gate-all-around, in which thin sheets of silicon were stacked horizontally and surrounded on all four sides by gate material, had been on the laboratory drawing boards for fifteen years. Samsung had pushed the first commercial gate-all-around device, which it called MBCFET, into volume production at its 3-nanometer node in June 2022. TSMC would follow at 2 nanometers in the middle of the decade. Each transition required new equipment, new materials, new defect modes, new process control, new design rules. None of it came cheap.

The R&D budgets behind the curve had risen to match. By 2024, TSMC was spending more than $6 billion a year on research and development alone, on top of capital expenditures that ran $30 to $40 billion annually and would reach $52 to $56 billion in 2026. Samsung spent something on the order of $24 billion across its full electronics business and was committing $15 billion a year specifically to its semiconductor operations. Intel, which had become by some measures the largest single R&D spender in the industry at $16.5 billion in 2023, was simultaneously losing money. The company’s foundry business alone had reported losses of $7 billion that year, and would replace its chief executive at the end of 2024 in the wake of the rising costs and stalled execution.

The numbers were not, considered in isolation, dispositive. A handful of companies could still afford them. TSMC’s customers were lining up for 3-nanometer capacity through 2026 and 2-nanometer capacity through 2028, paying $20,000 a wafer at three and over $30,000 a wafer at two, and the fabs were full. The economics, for Apple and Nvidia and AMD and Qualcomm, still closed. They closed because each company was selling its chips into end markets like phones, data centers, gaming GPUs, and AI training accelerators, in volumes large enough to amortize the half-billion-dollar design costs and the twenty-thousand-dollar wafers across products that retailed for hundreds or thousands of dollars apiece. For everyone else, the leading edge had become inaccessible. A startup designing a custom AI chip in 2025 was looking at a $150 million capital raise just to clear the design and tape-out phase, and a TSMC slot it would have to negotiate against the planet’s most demanding customers.

The political consequence of the second slope was not yet fully visible at the moment Chang gave his Bloomberg interview. It would take five more years, an American export-control regime, and a ground war to clarify it. But the structural answer was already obvious to anyone who had been paying attention. There were three logic foundries left at the leading edge. There were three memory makers. There was one EUV vendor. The capex curve was steepening, the design curve was steepening, and the survivors had become so few that any one of them, removed from the system, could not be replaced inside a decade. The industry that Moore and Rock had argued about over an Intel boardroom table in 1975, when the shape of the second slope had first become visible, was now an industry in which a single $20 billion factory in Tainan, or Pyeongtaek, or Hillsboro could not be left to fail. Whatever else the next chapters of the chip war would be about, they would be about that.

What Moore had said at SPIE in February 1995 had quietly become the operating reality. The rate of technological progress was being controlled from financial realities. The financial realities were no longer something individual companies could absorb. They had become something that rearranged the world.