TSMC's Grand Alliance

In the late summer of 2009, Morris Chang, who had retired from the chief executive job at Taiwan Semiconductor Manufacturing Company three years earlier, returned to it. He was seventy-eight years old. He still wore the dark suits and starched white shirts of an IBM man, which he had once been, and he still carried an unlit pipe in one breast pocket as a kind of prop. He had come back because the company was in the middle of an emergency that nobody else inside the building seemed equipped to handle.

The emergency was a process node. TSMC’s 40-nanometer line, the one that was meant to carry the company through the crisis years and prove its ability to keep pace with Intel, was running at yields nobody would say out loud in the cafeteria. By internal accounts that later leaked to the trade press, defect-free die counts on some early 40nm runs had bottomed in the twenties, with the best wafers climbing into the thirties. Inside a foundry, that was not a slow start. That was a smoking hole. Nvidia and Advanced Micro Devices were the two largest customers on the line. Both had bet their next-generation graphics roadmaps on the node, and both were now staring at empty channels and angry retailers.

Chang flew to California to see Jensen Huang in person. He had known Huang since the mid-1990s, when Huang had been running a graphics startup that nearly went under before its first products hit the market. By the account of a Digitimes reconstruction published years later, the older man sat down with Huang and offered hundreds of millions of dollars in compensation, with a forty-eight-hour deadline to accept. Huang took it. Lisa Su was not yet running AMD; the company that took the longer hit was the one she would inherit, and AMD’s discrete graphics share, which had hovered near forty-five percent before the crisis, slid below twenty and stayed there for years. The contrast was the point. The 40nm crisis was not a story about manufacturing physics, although the physics were genuinely hard. It was a story about which customers TSMC was willing to bleed for, and which had been brought into the inner ring of the company in a way that made bleeding for them feel like protecting itself. By the autumn of 2009, when Chang sat with Huang in Santa Clara, the inner ring had a name. TSMC called it the Open Innovation Platform.

The platform had been announced eighteen months earlier, in April 2008, while Rick Tsai was still the chief executive and Chang was still nominally retired. The name was deliberately bland, on purpose. What it described was not a single product or a single program but a category of work that the foundry industry had been doing piecemeal for a decade and that TSMC, alone among the foundries, had decided to formalize, brand, and run as a coherent strategy. The platform was the architecture of how a chip designer in Sunnyvale or Hsinchu actually got a design from a whiteboard sketch into a finished wafer at a TSMC fab in Taiwan, the connective tissue between the foundry and everything that surrounded it. TSMC’s bet, by 2008, was that this connective tissue mattered as much as the silicon.

To understand why the bet was overdue, it helped to look at what had happened to chip design between 2002 and 2008. In 2002, designing a complex system-on-chip at the 130-nanometer node was a serious undertaking but a tractable one. A team of perhaps forty engineers at a fabless company could integrate a processor core, a memory controller, an analog block or two, a handful of standard interfaces, and tape the result out to a foundry in twelve to eighteen months. By 2008, at 45 nanometers and approaching 40, the same chip might require two hundred engineers, two thousand pieces of pre-existing intellectual property licensed from twenty different vendors, three or four electronic design automation tool flows from competing software companies that did not natively talk to each other, and a process design kit, the file that translated the foundry’s manufacturing rules into things the design tools could check, that ran to hundreds of megabytes of dense, error-prone data. Each new node compressed the schedule, multiplied the verification burden, and added new physical effects that the design tools had to model. The transistor count per chip kept climbing. The number of human beings who could fit inside a single design team did not.

What was happening was that the design side of the industry, the side that TSMC depended on for revenue, was running into the same scaling crisis the manufacturing side had been worrying about for a decade. Process complexity had become design complexity. And the longer it took designers to finish a tape-out, the longer TSMC’s freshly built fab sat under-utilized, depreciating at the rate that all multi-billion-dollar capital equipment depreciated whether it was running wafers or not. Mark LaPedus and other industry chroniclers later quoted internal TSMC analysts who put the gap, by the mid-2000s, at six to twelve months between when the foundry wanted a new node loaded with paying tape-outs and when the customer base could realistically deliver. Six to twelve months on a five-billion-dollar fab was not a rounding error. It was the difference between a successful node and a financial wound.

The architect that TSMC handed the problem to was Cliff Hou. Hou was a Taiwanese engineer who had joined TSMC in 1997 and had spent the next decade quietly building the unglamorous internal organization that produced the foundry’s process design kits and reference design flows. He was not a charismatic public figure. He preferred to give technical talks. He had run, since the early 2000s, the small group inside TSMC that talked to the EDA companies, to the IP vendors, and to the design service houses, smoothing out the seams in the toolchain so that customers spent less time fighting their software and more time taping out. By 2008 he had been doing that work for ten years, and he had concluded that the seams were no longer something a foundry could smooth in its spare time. They needed to be the foundry’s core product, sold and supported with the same seriousness as the wafers themselves.

Hou’s solution, championed up the chain to Tsai and Chang, had several components, each of which solved a specific frustration that someone in the design world had been complaining about for years. The first was the iPDK, an interoperable process design kit, developed in concert with an industry consortium that TSMC had joined as the first major foundry. Until then, every EDA vendor needed its own version of a foundry’s process kit, which meant the foundry had to maintain three or four parallel kits, each one a vector for bugs. The iPDK was a single canonical kit, written against an industry-standard data model, that ran inside any of the major design environments. It eliminated weeks of debugging at the customer’s end and cut TSMC’s own internal kit-development burden in half. The second component was the Reference Flow, which by 2008 was at version 9.0, an end-to-end recipe that walked a designer through every step from synthesis to tape-out using qualified tools from the major EDA vendors, with each combination stress-tested against TSMC’s process and signed off at the foundry’s expense. The third was the silicon-proven IP library, a curated catalog of pre-existing functional blocks, processor cores, memory compilers, high-speed interface controllers, that had each been fabricated on a TSMC node, characterized for performance, and certified to work in combination with the others. By the time of the 2010 platform extension, S.T. Juang, then senior director of design infrastructure marketing, was pointing to thirty EDA partners, thirty-eight IP partners, twenty-three design center alliance partners, and nine value-chain aggregators all formally enrolled. The formal label for the whole thing, when Tsai and Chang announced it at TSMC’s spring symposium, was the Open Innovation Platform. Inside the company, people sometimes called it the OIP. Outside, the trade press called it the design ecosystem. They were the same thing.

What made the platform strategically interesting was less its individual components, most of which any other foundry could have copied, than the way TSMC organized the relationships around them. The phrase Chang began using publicly, by 2012, was Grand Alliance. He gave the most-quoted version of the speech that year at TSMC’s annual Supply Chain Management forum in Hsinchu, in front of an audience that included representatives from the EDA companies, the IP houses, the chemical and materials suppliers, the equipment vendors, and the largest fabless customers. Cooperating to co-create value, Chang said, was what the alliance was for. The world is an oyster, he told them, and it’s ours; let us grab the opportunity together. The line was a little cornier than Chang’s usual register and he allowed himself the indulgence because the room was already on his side. In the same address he made the point that defined the strategic posture for the next decade: the combined research-and-development spending of TSMC and its ten largest customers, taken together, exceeded the combined R&D budgets of Samsung’s chip business and Intel. The Grand Alliance was Chang’s way of saying that the foundry model could outspend the integrated device manufacturers, but only if the foundry remembered that it was not, by itself, a complete competitor. Its competitive unit was the alliance.

The argument had a corollary that competitors were slow to absorb. TSMC’s Pure Play Foundry pledge, the foundational promise that the company would never compete with its customers, had often been read in the West as a piece of corporate humility, a renunciation of upstream design ambitions in exchange for downstream manufacturing scale. Inside TSMC, Chang and his successors understood it as the opposite, as the precondition for the platform. An EDA vendor could not co-develop a reference flow with a foundry that was also designing chips that competed with the customers using that flow. An IP company could not hand over the source code of its highest-value cores to a foundry that might one day decide to integrate similar functions into its own product. A fabless customer could not safely share the netlist of an unannounced next-generation processor with a foundry that had a fabless arm. By forswearing design forever, TSMC made itself the only counterparty to which the rest of the design world could open its books. The platform was not despite the no-compete; the platform was because of the no-compete.

Once the platform existed, and once the alliance was named, the math began to compound in a particular way. Each new design that taped out on a TSMC node added to the body of silicon-proven IP that the next designer could license. Each new bug fix on a reference flow improved the toolchain that every subsequent customer would download. Each successful tape-out gave the EDA companies fresh data on which corner cases they had missed, data that could be folded back into the next release. The IP Alliance, which by some TSMC accountings had grown from roughly twenty-five partners in 2008 to thirty-nine by the early 2020s, expanded the catalog of available cores from around fifteen hundred to more than seventy thousand. By 2023, when the company celebrated the platform’s fifteenth anniversary, TSMC was citing more than fifty thousand active IP titles, forty-three thousand technology files, and roughly twenty-eight hundred process design kits across its full range of nodes from 0.25-micron legacy through 2-nanometer leading edge. The numbers would have been impressive on their own. What made them strategic was that they were not numbers a competitor could acquire. They were numbers a competitor would have to grow.

That was the asymmetry the rest of the industry kept underestimating. A new foundry could buy lithography scanners. It could hire process engineers and build clean rooms. What it could not do, by writing checks, was conjure into existence a population of customers who had spent the previous fifteen years debugging their netlists against its specific process kits and integrating its specific qualified IP into their products. That population was the platform. It existed inside the heads and the laptops and the version-control systems of the design teams at Apple, Nvidia, Qualcomm, AMD, MediaTek, Broadcom, Marvell, and several hundred smaller fabless houses, and it had been built, design-cycle by design-cycle, since the late 1990s. The accumulated co-design effort was the lock-in. Customers were not held by contracts; they were held by sunk cost. To move a complex chip from TSMC’s 5-nanometer process to a competitor’s nominally equivalent 5-nanometer process, the design team would have to swap process design kits, requalify dozens of pieces of foundation IP against the new rules, re-verify the whole chip against a different set of physical models, and accept that the first silicon back from the new fab would almost certainly carry surprises that would require respins. Industry estimates of the cost ranged in the high tens of millions of dollars per chip and twelve to eighteen months of schedule. For a leading-edge product whose entire commercial life was eighteen to twenty-four months, the math did not pencil.

Samsung tried to build a parallel ecosystem, called the Semiconductor Advanced Foundry Ecosystem, or SAFE, structured along similar lines: an EDA alliance, an IP alliance, design service partners, a multi-die integration program for advanced packaging. The structure was a faithful imitation. By the early 2020s, by Samsung’s own published numbers, the SAFE ecosystem had assembled more than thirty-six hundred IP titles and around eighty certified EDA tools. Compared with TSMC’s seventy thousand and counting, the gap was not narrowing. It was a gap of generations of accumulated tape-outs, and it told a story about the foundry business that the trade press did not always make explicit: that the foundry leader’s lead in process technology was the visible part of an iceberg whose underwater mass was the design ecosystem.

Intel tried something more dramatic. In July 2022, eighteen months into Pat Gelsinger’s bid to remake Intel into a contract manufacturer, Intel hired Suk Lee, the senior director who had run TSMC’s design infrastructure marketing for over a decade and had been, alongside Hou, one of the people most responsible for the operational guts of the OIP. Lee had joined TSMC in 2009, after stints at Synopsys, Cadence, and Texas Instruments, and had spent thirteen years inside the partner relationships, the symposium logistics, the IP qualifications, and the EDA negotiations. Intel made him a vice president and gave him the new title of head of an Ecosystem Technology Office inside Intel Foundry Services. The trade press read the hire as a serious signal. Inside Hsinchu, the reading was less worried, because the people at TSMC understood something that Intel’s investors did not, which was that an ecosystem is not a person. An ecosystem is the residue of fifteen years of relationships among hundreds of organizations that have learned to coordinate their release schedules, their bug-tracking systems, their roadmap reviews, and their shared customers. Bringing one executive across the Pacific did not transfer the residue. It transferred only the diagram of the residue. Three years on, Intel Foundry Services would still be courting fabless customers one at a time, lobbying the EDA majors to backport features, and trying to assemble an IP library that was a small fraction of the catalog its principal competitor had spent two decades curating.

The most candid summary came from a customer. Jensen Huang, by then running the most valuable semiconductor company in the world and shipping nearly all of it through TSMC, was asked at one industry forum to compare his foundry partner with the integrated device manufacturer that had once dominated American chipmaking. Huang’s answer became one of the most-quoted lines in the post-2020 chip discourse, repeated and amplified at semiconductor symposia from Hsinchu to San Jose. TSMC, he said, had learned to dance with four hundred partners. Intel had always danced alone. Morris Chang himself, by then ninety-two and giving valedictory keynotes at industry forums, repeated the line approvingly when asked. He said it captured the difference exactly.

The line captured something else, too, that the chip industry would spend the rest of the 2020s coming to terms with. The single most consequential business decision of the foundry era, the one Chang had made in the late 1980s when he committed the company to manufacturing only and forever, had not just defined TSMC’s product strategy. It had defined the kind of company TSMC could become as the design world fragmented into hundreds of fabless specialists, each with its own partial competence, each needing a counterparty that could pull the parts together. The Open Innovation Platform was the institutional embodiment of that counterparty. The Grand Alliance was the political embodiment. Together, they made TSMC less a manufacturer than a coordination engine, and more a coordination engine than any other manufacturer in the world. By the time the export controls of the late 2010s and the geopolitical fights of the 2020s would force every government and every CEO to ask whether TSMC could be replaced, the answer to that question would not be about lithography scanners or fab buildings. It would be about whether the rest of the industry was prepared to spend fifteen years rebuilding what it had taken TSMC fifteen years to grow.

Cliff Hou, by then deputy co-chief operating officer, kept giving the technical keynotes. The platform kept absorbing new partners. The IP catalog kept growing. The dance kept going. And whoever was watching from the other side of the dance floor, whether at Samsung in Suwon or Intel in Santa Clara, was discovering that watching was not the same as joining.